DCVS circuits are logic circuits implementable in today's CMOS (complementary metal oxide semiconductor) technology. As described in U.S. Pat. No. 4,570,084 to W. R. Griffin et al, such circuits may be formed out of arrays of many "trees" units (hereafter termed "trees"), each tree performing an elementary logical function. Each tree receives a number of binary data input signals, and generates a binary output data signal that represents a predetermined logical function of its inputs. In each tree, this function may be any one of many possible functions.
A tree generally contains two discrete circuit sections; a logic section and a load section. Each section contains pairs of switch elements having complementary associations and requiring the logic section to receive true and complement phases of each input signal simultaneously. Since each tree output may be applied to inputs of other trees, the load section must generate true and complement phases of the output signal simultaneously.
Inputs to any tree originate as outputs of other circuits (other trees, and/or other non-DCVS circuits on the same chip, and/or off-chip sources), and output of any tree is transferable as a data input to other circuits (other trees and/or other non-DCVS circuits on the same chip or off-chip circuits).
Arrays of many trees may be formed into sophisticated logic circuit devices (e.g. parallel adders, state machines, etc.). Operations of such arrays are controlled by discretely phased clock signals which alternately induce precharge and validation effects in the individual trees. During precharge, a pair of circuit nodes in the tree charge to a reference potential. During validation one of these nodes discharges, depending upon the immediate states of data inputs to the respective logic section. Potentials at the charged and discharged nodes establish the complementary phases of the tree output data signal. These potentials are transiently latched by the load circuit until the next precharge.
In constructing a DCVS circuit device, a semiconductor chip is processed to form basic configurations of many "unpersonalized" trees (switch elements without connections defining their logical interaction), and circuit connections are formed in and between the trees to establish the logical personality (functions) of the trees and the device. These connections power the tree circuits and carry data signals to and between trees.
A desired objective has been to make such unpersonalized configurations and their processes of personalization so uniform and simple that they can be handled in a manner analogous to the way in which today's gate arrays are made. This would permit a single unpersonalized configuration to be used as a common element in construction of many different types of circuit devices, and also would simplify the design and development of customized devices.
A problem with "gate array" handling of prior art DCVS tree arrays is the requirement to provide latch circuits between trees, at array positions which may vary according to specific logic requirements (i.e. at positions which are not predeterminable or even easily determinable). Some latch circuits may be needed to synchronize data flow between groups of trees (refer for instance to U.S. Pat. No. 4,615,010 to J. W. Davis et al). Others may be needed as shift register latch (SRL) elements to facilitate testing of trees (this is disclosed in co-pending US patent application by J. Babakanian et al Ser. No. 07/711,466--hereafter, the Babakanian et al '466 application--filed Jun. 5, 1991 and assigned to the assignee of the present application).
A problem with the placement of such latch circuits on a densely populated chip is that these circuit tend to alter the symmetry of the logic tree array, and thereby tend to complicate the design of DCVS circuits in "gate array" fashion. Also, some latches do not perform any logical function, and occupy space that otherwise could be serving a logical purpose.
The present invention seeks to overcome these prior art limitations by providing a basic tree structure that can be configured in uniform arrays, and adapted at any array coordinates to perform logic and/or latching functions.